Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications

Serial input/output (I/O) data rates are increasing in order to support the explosion in network traffic driven by big data applications such as the Internet of Things (IoT), cloud computing and etc. As the high-speed data symbol times shrink, this results in an increased amount of inter-symbol interference (ISI) for transmission over both severe low-pass electrical channels and dispersive optical channels. This necessitates increased equalization complexity and consideration of advanced modulation schemes, such as four-level pulse amplitude modulation (PAM-4). Serial links which utilize an analog-to-digital converter (ADC) receiver front-end offer a potential solution, as they enable more powerful and flexible digital signal processing (DSP) for equalization and symbol detection and can easily support advanced modulation schemes. Moreover, the DSP back-end provides robustness to process, voltage, and temperature (PVT) variations, benefits from improved area and power with CMOS technology scaling and offers easy design transfer between different technology nodes and thus improved time-to-market. However, ADC-based receivers generally consume higher power relative to their mixed-signal counterparts because of the significant power consumed by conventional multi-GS/s ADC implementations. This motivates exploration of energy-efficient ADC designs with moderate resolution and very high sampling rates to support data rates at or above 50Gb/s. This dissertation presents two power-efficient designs of ≥25GS/s time-interleaved ADCs for ADC-based wireline receivers. The first prototype includes the implementation of a 6b 25GS/s time-interleaved multi-bit search ADC in 65nm CMOS with a soft-decision selection algorithm that provides redundancy for relaxed track-and-hold (T/H) settling and improved metastability tolerance, achieving a figure-of-merit (FoM) of 143fJ/conversion step and 1.76pJ/bit for a PAM-4 receiver design. The second prototype features the design of a 52Gb/s PAM-4 ADC-based receiver in 65nm CMOS, where the front-end consists of a 4-stage continuous-time linear equalizer (CTLE)/variable gain amplifier (VGA) and a 6b 26GS/s time-interleaved SAR ADC with a comparator-assisted 2b/stage structure for reduced digital-to-analog converter (DAC) complexity and a 3-tap embedded feed-forward equalizer (FFE) for relaxed ADC resolution requirement. The receiver front-end achieves an efficiency of 4.53bJ/bit, while compensating for up to 31dB loss with DSP and no transmitter (TX) equalization

Effects of photoperiod on body mass, thermogenesis and body composition in Eothenomys miletus during cold exposure

Many small mammals respond to seasonal changes in photoperiod by altering body mass and adiposity. These animals may provide valuable models for understanding the regulation of energy balance. In present study, we examined the effect on body mass, rest metabolic rate, food intake and body composition in cold-acclimated (5 °C) in Eothenomys miletus by transferring them from a short (SD, 8h :16h L: D) to long day photoperiod (LD, 16h: 8h L:D). During the first 4 weeks of exposure to SD, E. miletus decreased body mass. After the next 4 weeks of exposure to LD, which the average difference between body masses of LD and SD voles was 4.76 g. This 14.74% increase in body mass reflected significant increases in absolute amounts of body components, including wet carcass mass, dry carcass mass and body fat mass. After correcting body composition and organ morphology data for the differences in body mass, only livers, kidney, and small intestine were enlarged due to photoperiod treatment during cold exposure. E. miletus increased RMR and energy intake exposure to LD, but maintained a stable level to SD after 28 days. Serum leptin levels were positively correlated with body mass, body fat mass, RMR as well as energy intake. All of the results indicated that E. miletus may provide an attractive novel animal model for investigation of the regulation of body mass and energy balance at organism levels. Leptin is potentially involved in the photoperiod induced body mass regulation and thermogenesis in E. miletus during cold exposure

Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications

Serial input/output (I/O) data rates are increasing in order to support the explosion in network traffic driven by big data applications such as the Internet of Things (IoT), cloud computing and etc. As the high-speed data symbol times shrink, this results in an increased amount of inter-symbol interference (ISI) for transmission over both severe low-pass electrical channels and dispersive optical channels. This necessitates increased equalization complexity and consideration of advanced modulation schemes, such as four-level pulse amplitude modulation (PAM-4). Serial links which utilize an analog-to-digital converter (ADC) receiver front-end offer a potential solution, as they enable more powerful and flexible digital signal processing (DSP) for equalization and symbol detection and can easily support advanced modulation schemes. Moreover, the DSP back-end provides robustness to process, voltage, and temperature (PVT) variations, benefits from improved area and power with CMOS technology scaling and offers easy design transfer between different technology nodes and thus improved time-to-market. However, ADC-based receivers generally consume higher power relative to their mixed-signal counterparts because of the significant power consumed by conventional multi-GS/s ADC implementations. This motivates exploration of energy-efficient ADC designs with moderate resolution and very high sampling rates to support data rates at or above 50Gb/s. This dissertation presents two power-efficient designs of ≥25GS/s time-interleaved ADCs for ADC-based wireline receivers. The first prototype includes the implementation of a 6b 25GS/s time-interleaved multi-bit search ADC in 65nm CMOS with a soft-decision selection algorithm that provides redundancy for relaxed track-and-hold (T/H) settling and improved metastability tolerance, achieving a figure-of-merit (FoM) of 143fJ/conversion step and 1.76pJ/bit for a PAM-4 receiver design. The second prototype features the design of a 52Gb/s PAM-4 ADC-based receiver in 65nm CMOS, where the front-end consists of a 4-stage continuous-time linear equalizer (CTLE)/variable gain amplifier (VGA) and a 6b 26GS/s time-interleaved SAR ADC with a comparator-assisted 2b/stage structure for reduced digital-to-analog converter (DAC) complexity and a 3-tap embedded feed-forward equalizer (FFE) for relaxed ADC resolution requirement. The receiver front-end achieves an efficiency of 4.53bJ/bit, while compensating for up to 31dB loss with DSP and no transmitter (TX) equalization

A cationic microporous metal–organic framework for highly selective separation of small hydrocarbons at room temperature

A new three-dimensional cationic metal–organic framework Zn8O(EDDA)4(ad)4•(HEDDA)2•6DMF•27H2O (ZJU-48; H2EDDA = (E)-4,4′-(ethene-1,2-diyl)dibenzoic acid; ad = adenine) was solvothermally synthesized and structurally characterized. ZJU-48 features a three-dimensional structure with a cationic skeleton and has one-dimensional pores along the c axis of about 9.1 × 9.1 Å2. The activated ZJU-48a exhibits a BET surface area of 1450 m2 g−1. The structural features of the charged skeleton of ZJU-48a have enabled its stronger charge-induced interaction with C2 hydrocarbons than with C1 methane, resulting in highly selective gas sorption of C2 hydrocarbons over CH4 with the adsorption selectivity over 6 at 298 K. The separation feasibility has been further established by the simulated breakthrough and pulse chromatographic experiments, thus methane can be readily separated from their quaternary mixtures at room temperature